(1) Field of the Invention
The invention relates to a method of preventing holes in a passivation layer, and more particularly, to a method of preventing holes in a passivation layer by metal layout in the fabrication of integrated circuits.
(2) Description of the Prior Art
The step coverage of the passivation layer on high aspect ratio metal lines is very poor--less than 40%. Also, keyhole type tunnels are formed between metal lines with spacing smaller than about 1 micrometer. These tunnels open up at metal line terminals, at points where the underlying metal layer is absent, and at turns in metal lines. During resist coating, the resist sinks into the underlying tunnels, making the resist layer thinner in these areas. The thinner resist generates holes in the passivation layer after pad etch which then degrades reliability. The sunken resist also causes a resist residue problem.
One of the temporary methods used to suppress the problem of holes in the passivation layer is to coat a thicker resist of between about 20,000 to 40,000 Angstroms in order to retain enough thickness of resist after the resist has sunk into the tunnels. The thickness is required to withstand the subsequent pad etching. The drawbacks of this solution are longer exposure time and longer resist stripping time. The resist residue problem still exists.
Other attempts have been made to resolve the problem. These include trapezoidally patterned metal lines to improve subsequent passivation step coverage and avoid the formation of keyholes, additional spin-on-glass coating to get a better passivation step coverage, using tetraethoxysilane (TEOS)/ozone based plasma enhanced chemical vapor deposited (PECVD) oxide as passivation, better planarization before the last metal layer, and implementation of chemical mechanical polishing (CMP), liquid phase deposition (LPD) oxide, or polyimide. All of these attempts suffer from process maturity, productivity, and complexity issues.
U.S. Pat. No. 5,032,890 to Ushiku et al describes the formation of dummy lines for improved next level coverage of an interconnection layer.